In serial data communication systems, data is transferred between a serial communication bus and devices, such as memory, terminals, under the control of a controlling processor. In order to ensure efficient data transfer, typically a plurality of communication channels are utilised for queuing data. A common method of managing the data queues is to map each queue into one of a plurality of First-In-First-Out (FIFO) memories.
In systems which are served by one processor, the plurality of communication channels are prioritized; a communication channel having a higher priority than another communication channel will be serviced by the one processor before the lower priority communication channels. Typically, the lower priority communication channels require larger FIFO memories, since the lower priority communication channels are serviced only after the higher priority communication channels have been serviced. The larger FIFO memories require greater silicon area which can be a significant disadvantage in some applications. Another disadvantage with such a priority scheme is that the design of the communication channels varies according to their respective priorities and so its implementation is not straight forward. Also, the speed of such priority schemes is limited.
Round Robin priority schemes which prioritize the servicing of the communication channels are also well known. Although such schemes allow the communication channels to be identical which helps to simplify the design, Round Robin schemes are significantly more complex to implement. A further disadvantage is that the Round Robin priority scheme is not suitable for some applications. For example, in applications where some communication channels need higher priority than the other communication channels in the communication system. This is the case when the communication channels support different data rates.